1. Field of the Invention
This invention relates to gallium arsenide (GaAs) very large scale integrated circuitry (VLSI). More particularly, this invention relates to depletion mode GaAs circuitry which is implemented in Schottky diode field effect transistor logic (SDFL).
2. Description of the Prior Art
A basic prior art GaAs inverter is shown and described in our above referenced co-pending application. The inverter shown was used to explain the problem of converting ECL signals to levels which could be employed with GaAs Schottky diode FET logic. The prior art inverter may be described as employing diode logic and gate driven transistor logic. Such prior art inverters are useful for inverting GaAs logic signals and may be employed in conjunction with the present invention.
Presently, GaAs logic may be divided into either enhancement mode or depletion mode technologies. Enhancement mode technology is adaptable to making very large scale integrated circuits (VLSI), but presents problems in the manufacture of the circuits. No enhancement mode GaAs logic circuits are yet commercially available. Enhancement mode logic is known to be a simple form of logic, but requires very difficult and precise processing in manufacturing of circuits of complexity greater than 50 to 100 gates.
This invention is concerned with depletion mode technology and more specifically with Schottky diode field effect transistor logic (SDFL). SDFL logic is functionally versatile, requires low power and is very fast and may be implemented in very large scale integrated circuits. Heretofore, SDFL logic was predominately based on diode logic and driving the gates of switching transistors.
It would be desirable to provide an improved GaAs depletion mode logic circuit that is completely compatible with prior art diode logic and gate driven logic but provides much higher density and requires fewer logic levels to perform the same prior art logic functions. By reducing the number of devices, the reliability of logic is increased, the manufacturing costs are decreased, speed is increased and less power is consumed to perform the same logic functions.